Closed Solicitation · DEPT OF DEFENSE
AI Summary
The Department of Navy is seeking information on establishing a U.S. on-shore production-level back end of line 300mm wafer fabrication capability for magnetic tunnel junction technology. This RFI aims to enhance national security and supply chain resilience for MRAM components, requiring ITAR compliance and various manufacturing capabilities. Responses will inform future solicitations and partnerships.
N0016425SNB93 – Request for Information: U.S. on-shore Production-Level Back End of Line 300mm Wafer Fabrication Capability for Magnetic Tunnel Junction Technology Supporting ITAR Flow – PSC 5961 – NAICS 334413
Issue Date: 12 September 2025 - Closing Date: 13 October 2025
Synopsis
The Department of Navy is seeking information from industry stakeholders, including capital equipment manufacturers, semiconductor tool suppliers, and intellectual property licensors related to establishing a U.S. on-shore back end of line (BEOL) 300mm wafer production fabrication capability for Magnetoresistive Random Access Memory (MRAM) devices utilizing magnetic tunnel junction (MTJ) technology, with a focus on production foundry capabilities. This request for information (RFI) aims to support production of MRAM components to enhance national security applications, supply chain resilience, and defense system architectures. At a minimum, the envisioned U.S. on-shore MTJ fabrication capability shall meet the following requirements:
The requirement for ITAR/CUI compliance is driven by the need for MRAM in radiation-hardened memory microcircuits custom-designed to meet specific natural space and man-made radiation environments.
For this request for information (RFI), we are seeking input from a broad range of institutions, including domestic semiconductor manufacturers, fabless chip design companies, capital equipment manufacturers, and other industry stakeholders with expertise in high-volume manufacturing and pure-play foundry capabilities, as well as academia, research institutions, and government labs with relevant research and development expertise. Please note that this RFI covers specific initiatives from the Department of Navy.
Responses of interest include those addressing:
Responses will inform potential future solicitations, partnerships, or funding opportunities under various initiatives to accelerate domestic manufacturing.
Background
The historical and ongoing evolution of MRAM technologies, from toggle MRAM to STT-MRAM to SOT-MRAM and others, is well documented, as is their various radiation test campaigns and demonstrated radiation hardness.[3][4][5][6][7]–[8] The US Government (USG) and the DIB have provided funding and have benefitted from this evolution. The DoD recognizes MRAM's role in simplifying architectures by reducing reliance on flash backups, enabling more straightforward and cost-effective state-saving mechanisms. Over the last 15+ years MRAM has been designed into various DoD critical systems, platforms and technologies, especially those having high-reliability and challenging radiation environment requirements.
However, in recent years, U.S. chip innovation has been threatened as next-generation hardware technologies have become increasingly reliant on offshore sources for State of the Art (SOTA) as well as State of the Practice (SOTP) manufacturing, prototyping, and innovation. This trend creates significant hurdles for the domestic microelectronics community.
Problem
For microelectronics generally and MRAM specifically, DoD must facilitate and promote development and qualification of components sufficient for DoD program of record adoption and transition. While the capital equipment upgrades enabling FEOL CMOS processing at 300mm wafer diameter have been undertaken over the last 15+ years both offshore and onshore, to date there have only been offshore upgrades for 300mm processing of the BEOL layers for MRAM. Given that advanced CMOS nodes have been developed with 300mm processes, support for 200mm processing equipment is fading, and ITAR manufacturing flow is often required for custom-designed MRAM devices for DoD applications, there is now a critical need for establishing a U.S. on-shore production-level BEOL 300mm wafer fabrication capability for MTJ technology supporting an ITAR manufacturing flow. Fulfillment of this need is necessary to maintain the United States’ strong position in the global technology race.
Information Sought
Minimum requirements for the envisioned capability are listed in the synopsis above. In terms of the foundry model, this RFI aims to cast a wide net intended to cover pure-play, IDM and split-fabrication models. Ideally the BEOL fabrication capability should be compatible with a variety of different CMOS technologies such as bulk transistor, FinFET, partially-depleted silicon-on-insulator (PD-SOI) and fully-depleted silicon-on-insulator (FD-SOI). The MTJ fabrication capability needs to cover a range of node sizes for different CMOS technology platforms, potentially ranging from as large as 90 nm down to 14 nm or smaller.
Although fabrication parameters for specific MTJ designs are proprietary to a short list of holders of IP and trade secrets, generally BEOL MRAM fabrication consists of MTJ layers comprised of free and reference magnetic layers separated by a tunnel barrier; electrode, spacer and cap layers; metal and via layers; and interlayer dielectric material which surrounds the above layers.
Many of these layers are comprised of materials that are not otherwise used in semiconductor manufacturing, and in response specialized processing equipment has been developed for MRAM fabrication, providing “30+ layers [and] 10+ materials in a single integrated system” with “sub-Angstrom uniformity”.[9],[10] Specialized equipment for MRAM processing will need to be combined with standard processing equipment (lithography, cleaning, plating, etc.) to achieve a complete solution.
RFI Questions (Note: Reply only to relevant questions. Not necessary to reply to all.)
Primary information of interests:
Secondary information of interests:
RFI Submission and Contact Information
In the RFI response, please provide your name(s), contact information, the company/entity and industry sector that the response represents.
Responses can be provided in word format as a white paper not to exceed ten pages. Responses will NOT be made public. Please provide answers to the RFI questions contained herein, and submit RFI response by 13 October 2025. Please reference Announcement Number: N0016425SNB93 with any response to this RFI.
If you have any questions about this RFI, please reach out to Mr. Eric McCord, at eric.t.mccord.civ@us.navy.mil or (812)854-8058.
Eligibility
The Department of Navy invites participation for this RFI to a broad range of institutions, including domestic semiconductor manufacturers, fabless chip design companies, capital equipment manufacturers, and other industry stakeholders with expertise in high-volume manufacturing and pure-play foundry capabilities, as well as academia, research institutions, and government labs with relevant research and development expertise.
Interested parties must be properly registered in the System for Award Management (SAM) and may obtain information on SAM registration and annual confirmation requirements by calling 1-866-606-8220 or via the internet at https://www.sam.gov.
Disclaimer
This RFI is the initiation of market research under FAR Part 10. This announcement does not constitute an Invitation for Bids (IFB), a Request for Quote (RFQ), or a Request for Proposal (RFP) and it should not be construed as a commitment of any kind by the Government to issue a formal solicitation or ultimately award a contract. Participation in this RFI is strictly voluntary.
Responses to this notice cannot be accepted as offers. The United States Government is in no way liable to pay for or reimburse any companies or entities that respond to this announcement. Any costs incurred by interested companies in response to this announcement will NOT be reimbursed. Nothing in this announcement constitutes an obligation on the part of the United States Government.
[1] See https://dodcio.defense.gov/CMMC/
[2] Coleman, Victoria. “NDAA 2023 Mandated Independent Review of USD (R&E) Microelectronics Quantifiable Assurance Effort.” (2023). Available online at: https://www.af.mil/Portals/1/documents/2023SAF/MQA_Report.pdf
[3] Katti, Romney R. "Magnetoresistive Random Access Memories for Space and Radiation-Hardened Applications." 2021 IEEE 32nd Magnetic Recording Conference (TMRC). IEEE (2021).
[4] Marinella, Matthew J. "Radiation effects in advanced and emerging nonvolatile memories." IEEE Transactions on Nuclear Science 68.5 (2021): 546-572.
[5] Ikegawa, Sumio, et al. "Magnetoresistive random access memory: Present and future." IEEE Transactions on Electron Devices 67.4 (2020): 1407-1419.
[6] Bagherzadeh, Nader, and Ozdal Boyraz. Radiation Characterization of STT-RAM Devices. No. DTRATR2218. 2022.
[7] Alamdar, Mahshid, et al. "Irradiation effects on perpendicular anisotropy spin–orbit torque magnetic tunnel junctions." IEEE Transactions on Nuclear Science 68.5 (2021): 665-670.
[8] Coi, Odilia, et al. "Proton irradiation effects on spin orbit-torque and spin transfer-torque magnetic tunnel junctions." RADECS 2021-21st European Conference on Radiation and its Effects on Components and Systems. 2021.
[9] “Applied Materials Enables Emerging Memories for the Internet of Things and Cloud Computing” (2019). Available online at https://ir.appliedmaterials.com/node/22826/pdf
[10] Chen, Wei. “New PVD Systems for Advanced Memory Applications.” AVS Thin Film Users Group (2019). Available online at https://nccavs-usergroups.avs.org/wp-content/uploads/TFUG2019/November2019/TFUG1119-4-AMAT-Chen.pdf
REQUEST FOR INFORMATION: U.S. ON-SHORE PRODUCTION-LEVEL BACK END OF LINE 300MM WAFER FABRICATION CAPABILITY FOR MAGNETIC TUNNEL JUNCTION TECHNOLOGY SUPPORTING ITAR FLOW is a federal acquisition solicitation issued by DEPT OF DEFENSE. Review the full description, attachments, and submission requirements on SamSearch before the response deadline.
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